An Integer Linear Programming Model of Software Pipelining for the MIPS R8000 Processor

In parallelizing the code for high-performance processors, software pipelining of innermost loops is of fundamental importance. In order to beneet from software pipelining, two separate tasks need to be performed: (i) software pipelining proper ((nd the rate-optimal legal schedule), and (ii) register allocation (allocate registers to the found schedule). Software pipelining and register allocation can be formulated as an integer linear programming (ILP) problem, aiming to produce optimal schedules. In this paper, we discuss the application of the integer linear programming to software pipelining on the MIPS R8000 super-scalar microprocessor. Some of the results were presented in the PLDI96 14], where they were compared to the MIPSpro software pipeliner. In this paper we further extend the ILP model for the MIPS R8000 by including memory optimization and present the entire model in detail.